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gr1hw.h.z
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gr1hw.h
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C/C++ Source or Header
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1992-04-03
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15KB
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428 lines
#ifndef __SYS_GR1HW_H__
#define __SYS_GR1HW_H__
/*
* sys/gr1hw.h -- GR1 Family Hardware Description
*
* Boards supported: GR1, GR1.5, VGR2, PGR
*
* $Revision: 1.22 $
*
* Copyright 1991, Silicon Graphics, Inc.
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
* the contents of this file may not be disclosed to third parties, copied or
* duplicated in any form, in whole or in part, without the prior written
* permission of Silicon Graphics, Inc.
*
*/
struct xmap2 {
volatile unsigned long int noop ;
volatile unsigned long int blue ;
volatile unsigned long int green ;
volatile unsigned long int red ;
volatile unsigned long int addrinc ;
volatile unsigned long int other ;
volatile unsigned long int addrhi ;
volatile unsigned long int addrlo ;
} ;
/*
* XPCs are only used on the MGR and AGR. They've been included because
* their addresses are reserved in the GR1 family's address space
*/
struct xpc {
volatile unsigned long int mxReg[4] ;
} ;
struct bt457_dac {
volatile unsigned long int addr ;
volatile unsigned long int color ;
volatile unsigned long int control ;
volatile unsigned long int overlay ;
} ;
struct gr1_824dac {
volatile unsigned long int dacReg[4] ;
} ;
struct bt431_cursor {
volatile unsigned long int addr0 ;
volatile unsigned long int addr1 ;
volatile unsigned long int glyph ;
volatile unsigned long int control ;
} ;
struct hq1 {
volatile unsigned long int clearstall ;
unsigned long int pad0[15] ;
volatile unsigned long int setss ;
unsigned long int pad1[15] ;
volatile unsigned long int clearss ;
unsigned long int pad2[15] ;
volatile unsigned long int executess ;
unsigned long int pad3[15] ;
volatile unsigned long int readpc ;
unsigned long int pad4[15] ;
volatile unsigned long int clearintr ;
unsigned long int pad5[15] ;
} ;
struct gr1_hw {
volatile unsigned long int ucstore[256] ; /* 0x0 */
struct xmap2 xmap[5] ; /* 0x400 */
struct xmap2 xmapAll ; /* 0x4A0 */
volatile unsigned long int displayReg1 ; /* 0x4C0 */
unsigned long int pad0[7] ; /* 0x4C4 */
volatile unsigned long int displayReg0 ; /* 0x4E0 */
unsigned long int pad1[7] ; /* 0x4E4 */
struct bt457_dac redDac ; /* 0x500 */
struct xpc xpc0 ; /* 0x510 */
struct bt457_dac greenDac ; /* 0x520 */
struct xpc xpc1 ; /* 0x530 */
struct bt457_dac blueDac ; /* 0x540 */
struct xpc xpc2 ; /* 0x550 */
struct bt431_cursor cursor0 ; /* 0x560 */
struct xpc xpc3 ; /* 0x570 */
struct bt431_cursor cursor1 ; /* 0x580 */
struct xpc xpc4 ; /* 0x590 */
volatile unsigned long int displayReg4 ; /* 0x5A0 */
unsigned long int pad2[3] ; /* 0x5A4 */
struct xpc xpcAll ; /* 0x5B0 */
volatile unsigned long int displayReg3 ; /* 0x5C0 */
unsigned long int pad3[3] ; /* 0x5C4 */
struct gr1_824dac rgbDac ; /* 0x5D0 */
volatile unsigned long int displayReg2 ; /* 0x5E0 */
unsigned long int pad4[23] ; /* 0x5E4 */
struct hq1 hq ; /* 0x640 */
unsigned long int pad5[16] ; /* 0x7C0 */
volatile unsigned long int fifo[256] ; /* 0x800 */
volatile unsigned long int HQaddrhi[128] ; /* 0xC00 */
volatile unsigned long int clrHQaddrMSB ; /* 0xE00 */
volatile unsigned long int setHQaddrMSB ; /* 0xE04 */
unsigned long int pad6[382] ; /* 0xE08 */
volatile unsigned long int dataram[256] ; /* 0x1400 */
unsigned long int pad7[512] ; /* 0x1800 */
volatile unsigned long int finish0 ; /* 0x2000 */
volatile unsigned long int finish1 ; /* 0x2004 */
unsigned long int pad8[(0x207c-0x2008)/4] ; /* 0x2008 */
/* register use to distinguish Gr1 vs Gr2 */
volatile unsigned long int GR1vsGR2; /* 0x207c */
unsigned long int pad9[(0x8000-0x2080)/4]; /* 0x2080 */
/*
* The following are registers found only on these variants of the GR1:
* - VGR2 (9U GR1, usable with either private bus or VME)
* - PGR (6U GR1)
* They are not mapped into a GL process's address map, since only
* the kernel manipulates them.
*/
/* board PAL initializes vgrIntrCfg correctly => no need to touch */
volatile unsigned long int vgrIntrCfg ; /* 0x8000 */
unsigned long int pad10[(0x100-4)/4] ; /* 0x8004 */
/* no need to touch this register when on private bus */
volatile unsigned long int vgrVmeReset ; /* 0x8100 */
unsigned long int pad11[(0x100-4)/4] ; /* 0x8104 */
/* signals are active low */
volatile unsigned long int vgrIsr ; /* 0x8200 */
unsigned long int pad12[(0x100-4)/4] ; /* 0x8204 */
/* 0 = disabled, 1 = enabled */
volatile unsigned long int vgrImask ; /* 0x8300 */
unsigned long int pad13[(0x100-4)/4] ; /* 0x8304 */
/* writing anything clears the vertical retrace interrupt */
volatile unsigned long int vgrVRIntrClr ; /* 0x8400 */
unsigned long int pad14[(0x100-4)/4] ; /* 0x8404 */
/*
* NOTE: This reg is defined at 0x85E0 instead of 0x8500 so
* that it overlaps display reg 2 on GR1. This allows us
* to write a probe routine that can tell the difference
* between a GR1 and VGR. The reg will respond the same
* at either address on the VGR.
* Otherwise, no need to touch this register when on private bus.
*/
unsigned long int pad15[0xE0/4] ; /* 0x8500 */
volatile unsigned long int vgrVmeIntrId ; /* 0x85E0 */
unsigned long int pad16[(0x100-0xE4)/4] ; /* 0x85E4 */
/* no need to touch this register when on private bus */
volatile unsigned long int vgrVmeDma ; /* 0x8600 */
/*
* each VGR2 and PGR board decodes an address range of 0x10000
* => sizeof(struct gr1hw) must be 0x10000
*/
unsigned long int pad17[(0x10000-0x8604)/4] ; /* 0x8604 */
} ;
/* RAMs */
/*
* Microcode RAM sizes in WORDs:
* MGR, AGR, PGR: 0x8000
* others: 0x4000
*/
#define DRAM_SIZE 0x2000 /* Data RAM size in WORDs */
/* HQ */
#define HQM_PG_SIZE 256 /* 256 long addressable area w/ HQM */
/*
* Bt431 Cursor chip
*/
#define CURS_GLYPH_SIZE 512 /* Number bytes in glyph */
/* Control register offsets */
#define CURS_CMD 0
#define CURS_XLO 1
#define CURS_XHI 2
#define CURS_YLO 3
#define CURS_YHI 4
#define CURS_WINXLO 5
#define CURS_WINXHI 6
#define CURS_WINYLO 7
#define CURS_WINYHI 8
#define CURS_WINWLO 9
#define CURS_WINWHI 10
#define CURS_WINHLO 11
#define CURS_WINHHI 12
#define CURS_XHOTOFF 31 /* offsets from origin to hotspot */
#define CURS_YHOTOFF 31 /* glyph 0,0 is lower left */
/* cursor magic offsets for 1280x1024 */
#define CURS_XOFF_1280 (0+246-57) /* D+H-P offset for Cx */
#define CURS_YOFF_1280 (39-32) /* V-32 offset for Cy */
/* cursor magic offsets for 1024x768 */
#define CURS_XOFF_1024 (0+126-57) /* D+H-P offset for Cx */
#define CURS_YOFF_1024 (43-32) /* V-32 offset for Cy */
/* cursor magic offsets for NTSC */
#define CURS_XOFF_NTSC -6 /* Determined empirically. */
#define CURS_YOFF_NTSC -554 /* Same */
/* cursor magic offsets for PAL */
#define CURS_XOFF_PAL 24 /* Determined empirically. */
#define CURS_YOFF_PAL -457 /* Same */
/* cursor magic offsets for 30HZ */
/* XXX CHECK THESE VALUES */
#define CURS_XOFF_30 39 /* Taken from Aspen values. */
#define CURS_YOFF_30 18 /* Same */
/* cursor magic offsets for STEREO */
/* XXX CHECK THESE VALUES */
#define CURS_XOFF_STEREO CURS_XOFF_1280 /* Taken from Aspen values. */
#define CURS_YOFF_STEREO (CURS_YOFF_1280+1) /* Taken from Aspen values. */
/* GR1 rev. A board defines - needed to determine curs offsets */
#define REVA_EADDRLO 0x69010000 /* Lowest rev. A board ethernet addr */
#define REVA_EADDRHI 0x6901001B /* Highest rev. A board ethernet addr */
#define CURS_XOFFREVA 309 /* x hardware offset Rev. A board */
/* Command register bits */
#define CURS_BLOCK 0x40 /* block cursor */
#define CURS_CROSS 0x20 /* Cross hair cursor */
#define CURS_FMT 0x01 /* if both block & cursor are enabled:*/
/* 0 - '^', 1 - '|' bits */
#define CURS_1TO1MUX 0x00 /* use 1:1 multiplexing */
#define CURS_4TO1MUX 0x04 /* use 4:1 multiplexing */
#define CURS_5TO1MUX 0x08 /* use 5:1 multiplexing */
#define CURS_1THICK 0x00 /* Cross hair is 1 bit thick */
#define CURS_3THICK 0x01 /* Cross hair is 3 bits thick */
#define CURS_5THICK 0x02 /* Cross hair is 5 bits thick */
#define CURS_7THICK 0x03 /* Cross hair is 7 bits thick */
/* XMAPs */
/* XMAP2 mode register bit defines */
#define XMAP_DISPLAY 0x7 /* Bits in mode reg to select display mode */
#define XMAP_BUFSEL 0x8 /* Bit in mode reg to select out buf */
#define XMAP_OVER 0xf0 /* Bits in mode reg to enable overlay planes */
#define XMAP_UNDER 0x100 /* Bit in mode reg to enable underlay */
#define XMAP_MULTIMAP 0x200 /* Bits in mode reg to enable multimap mode */
#define XMAP_MAPNUM 0x3C00 /* Bits in mode reg for multimap map number */
#define XMAP_MMAP_SHIFT 10 /* bits to shift up map before or-ing in */
/* garbage !! who needs this incorrect define ??? */
#define XMAP_MAPSEL 0x3C /* Bits in mode reg for multimap map number */
/* XMAP2 mode register display mode defines */
#define XMAP_8CI 0x0 /* 8 bitplane, 8-bit color index */
#define XMAP_8DCI 0x1 /* 8 bitplane, 4-bit double buffered color index */
#define XMAP_24DCI 0x2 /* 24 bitplane, 12-bit double buffered color index*/
#define XMAP_24RGB 0x4 /* 24 bitplane, 24-bit RGB */
#define XMAP_24DRGB 0x5 /* 24 bitplane, 12-bit double buffered RGB */
#define XMAP_MODEREG_OFF 0
#define XMAP_WIDAUX_OFF 32
#define XMAP_DREG_OFF 33
#define XMAP_NXMAP 5 /* Number XMAP2's */
#define XMAP_NCOLMAPENT 4096 /* Number col map entries */
#define XMAP_NAUXMAPENT 16 /* Number aux col map entries */
#define XMAP_NMULTIMAP 16 /* Number multimaps */
#define XMAP_NMODEREGS 16 /* # of entries in mode reg table */
#define XPC_NMODEREGS 4 /* # of entries in mode reg table */
#define XMAP_COLSEL 0x1000 /* bit set in A reg to select col tbl */
/* DACs */
#define DAC_CMDMASK (0x3 << 2) /* DAC Mask to get command */
#define DAC_AREG (0x0 << 2) /* DAC op: RW addr reg */
#define DAC_COL (0x1 << 2) /* DAC op: RW color palette RAM */
#define DAC_CR (0x2 << 2) /* DAC op: RW control reg.s */
#define DAC_OVRLAY (0x3 << 2) /* DAC op: RW overlay color */
#define DAC_READMASK 0x4 /* offset of read mask */
#define DAC_BLINKMASK 0x5 /* offset of blink mask */
#define DAC_CMD 0x6 /* offset of command register */
#define DAC_TEST 0x7 /* offset of test register */
#define DAC_NGAMMAENT 256 /* Number gamma ramp entries */
#define DAC_NOVLMAPENT 4 /* Number overlay map entries */
/* DAC command register bit settings: */
#define DAC_5TO1MUX 0x80 /* use 5:1 multiplexing */
#define DAC_RAMENBL 0x40 /* Use RAM if over bits are 0 */
#define DAC_BLINK0 0x00 /* blink rate 0: 1.024(75/25) */
#define DAC_BLINK1 0x10 /* blink rate 1: 0.512(50/50) */
#define DAC_BLINK2 0x20 /* blink rate 2: 1.024(50/50) */
#define DAC_BLINK3 0x30 /* blink rate 3: 2.048(50/50) */
#define DAC_OL1BENBL 0x08 /* OL1 Blink Enable */
#define DAC_OL0BENBL 0x04 /* OL0 Blink Enable */
#define DAC_OL1ENBL 0x02 /* OL1 Enable */
#define DAC_OL0ENBL 0x01 /* OL0 Enable */
/* Display registers */
#define NDREG 5 /* Number of display reg's */
/* REG 0 */
#define DREG_GRF1EN 0x01 /* Bit to enable GRF1 board,
disable for RE2 (LOW ENABLED) (reg 0) */
#define DREG_ZBUF0 0x08 /* Status bit: Z-buffer installed
(LOW ENABLED) (reg 0) -- MGR only */
#define DREG_SMALLMON0 0x08 /* Status bit: small monitor installed
(LOW ENABLED) (reg 0) -- non MGR */
#define DREG_PGROUTBIT 0x04 /* PGR is characterized by DREG0 CR2 being
routed back to CR4 */
#define DREG_PGRINBIT 0x10
/* REG 1 */
#define DREG_SYNCGRN 0x01 /* Bit to enable composite SYNC on Green
(LOW ENABLED) (reg 1) */
#define DREG_MONITORMSBMASK 0x06 /* MSBs of monitor type (rest in reg4) */
#define DREG_TURBO 0x08 /* Status bit: turbo option installed
(LOW ENABLED) (reg 1) */
#define DREG_OVRLAY0A 0x10 /* Status bit: DAC overlay bit 0 bank A
(reg 1) */
/* REG 2 */
#define DREG_SCREENON 0x01 /* Bit to turn screen on (reg 2) */
#define DREG_UNCOM2 0x02 /* Uncommitted bit to xilink (reg 2) */
#define DREG_LEDOFF 0x04 /* Bit to turn off LED (reg 2) */
#define DREG_BITPLANES 0x08 /* Status bit: extra bitplanes installed
(LOW ENABLED) (reg 2) */
#define DREG_ZBUF 0x10 /* Status bit: Z-buffer installed
(LOW ENABLED) (reg 2) -- non MGR */
/* REG 3 */
#define DREG_GENSTATEN 0x01 /* enable status out of genlock connector*/
#define DREG_LSBBLUE_OUT DREG_GENSTATEN
/* Buffer or latch the blue LSB output
* This feature exists only on VGR and is
* in place of DREG_GENSTATEN */
#define DREG_LCARESET 0x02 /* Bit to reset LCA
(LOW ENABLED) (reg 3) */
#define DREG_MONITORRESET 0x04 /* Bit to reset monitor type (reg 3) */
#define DREG_FIFOEMPTY 0x08 /* Status bit: FIFO empty
(LOW ENABLED) (reg 3) */
#define DREG_FIFOFULL 0x10 /* Status bit: FIFO 1/2 full
(LOW ENABLED) (reg 3) */
/* REG 4 */
#define DREG_MONITORMASK 0x03 /* Mask for LSBs of monitor type (reg 4) */
#define DREG_EXTCLKSEL 0x04 /* Bit to select external clock (reg 4) */
#define DREG_MEGOPT 0x08 /* Status bit: 1Meg Video RAMs installed
(reg 4) */
#define DREG_GESTALL 0x10 /* Status bit: GE stalled
(LOW ENABLED) (reg 4) */
#define DREG_ACLKEN 0x20 /* Bit to enable clock asynchronously
(reg 4) */
#define DREG_SCLKEN 0x40 /* Bit to enable clock synchronously
(reg 4) */
/* Monitor bits (for reg 1 and reg4) */
#define DREG_MONITOR60HZ 0x00 /* Monitor type 60Hz 1280x1024 */
#define DREG_MONITOR30HZ 0x01 /* Monitor type 30Hz 1280x1024 */
#define DREG_MONITORNTSC 0x02 /* Monitor type NTSC 645x485 */
#define DREG_MONITORPAL 0x03 /* Monitor type PAL 780x575 */
#define DREG_MONITORSTEREO 0x04 /* Monitor type 120HZ 1280X512X2 */
/* these are specific to VGR, but should be place holders for GR1 */
#define DREG_LSBBLUE_LATCH 0x05 /* set mode of blue LSB out to vmux/cg */
#define DREG_LSBBLUE_BUF 0x06 /* set mode of blue LSB out to vmux/cg */
#define DREG_MONITORMED60HZ 0x0f /* Monitor type 60HZ 1024X768 */
/*
* Bits in the vgrIntrCfg register--
*/
#define VGR_HDMA_EN 0x1 /* active low host dma enable bit, given
* to the board that is allowed on the bus
*/
/*
* Bits in VGR and PGR interrupt status and mask registers vgrIsr and
* vgrImask. The bit assignments are the same for both registers, so
* there's no need for separate defines. vgrIsr signals are active low.
* In vgrImask, 0 = disabled, 1 = enabled.
*/
/* active low */
#define VGR_VR 0x004 /* Vertical retrace interrupt */
#define VGR_GE 0x040 /* GE interrupt */
#define VGR_FIFO 0x080 /* FIFO full interrupt */
#define VGR_VRSTAT 0x200 /* Vertical retrace status (not an
* interrupt) -- only in vgrIsr */
#endif /* __SYS_GR1HW_H__ */